1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to mechanisms for debugging integrated circuits.
2. Description of the Related Art
Integrated circuits (ICs) and electronic assemblies are typically tested prior to shipping to a customer. One such testing mechanism developed for testing connections of ICs to printed circuit boards (PCB's) is known as boundary scan. Boundary scan testing is based on the IEEE 1149.1 Standard, which is commonly known as Joint Test Action Group (JTAG). Although originally developed for boundary scan testing, the uses of the JTAG architecture have expanded in recent years. For example, JTAG ports are sometimes used to access internal functional blocks of an IC for testing. Moreover, the use of JTAG access ports has been further expanded for use in debugging IC designs as well as software designed to execute on such ICs.
The expanding use of JTAG access ports has spurred further development in providing internal access to ICs. Many ICs now include a debug port (DP) having multiple JTAG access ports coupled to various internal components. The DP may also include one or more serial wire port (SWPs), memory access ports, and other types of ports that enable the accessing of internal IC functional blocks for debugging purposes. Such access ports convey various signals to accessible functional blocks, including data signals and clock signals. For example, test input data, clock, and mode select signals may be conveyed to a functional block through a JTAG port, while test output data may be received through the JTAG port. Some ICs, such as processors, may also include debug registers. Such debug registers may be programmed by executing processor code in a processor core.